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Preliminary W62410 DSP CONTROLLER FOR TAD
GENERAL DESCRIPTION
The W62410 chip is a digital speech signal processor. The W62410 implements the STREAMTALKTM speech compression, voice prompt processing, telephone line signal processing, AFlash and DRAM memory management and 16 I/O lines all in one chip for a fully digital answering machine. The W62410 acts as a slave processor to its host. The W62410 can be driven through a serial bus or an 8 bit parallel bus allowing the possibility for both 4 bit and 8 bit micro controllers to be used. Since the W62410 is a slave to the host, the host is responsible for activating and deactivating all the functions the W62410 provides.
FEATURES
* 24.576 MIPS for CHIPSET core and 24.576 MHz crystal used.
*
Internal Voice Prompt ROM, 16K x 16 (256 KBits), which can be optionally swapped to an external Winbond proprietary serial OTP Message Storage Option. and refresh ability.
* Support for up to four times 1M x 4 or one 4M x 4 types DRAM for up to 16 Mbits storage space * Support for up to four times Samsung KM29N040T, 512K x 8, NAND Flash for up to 16 Mbits of
storage space.
* Support for up to four times Samsung KM29N1600T, 2M x 8, NAND Flash for up to 64 Mbits of
storage space.
* Serial or 8-bits parallel C interface supported. * One CODEC interface (Law codec such as the TP3054). * Sixteen available I/O lines. Individually programmable as an input or output line. * No external SRAM needed. * Real Time Clock supports Weekday/Hour/Minute. * The RTC keeps running while in Power down mode (using a 32.768 KHz crystal). * Low Power Consumption and Power down mode support. * Fully static design. * Packaged in 100-pin PQFP
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Publication Release Date: April 2000 Revision A1
Preliminary W62410
PIN CONFIGURATION
The W62410 is available in a 100 pin PQFP package.
I VO S1 S5
I O 1 4
III OOO 111 321
O T P D I O I I I V I I I I I I I WR V A 4 1OOO DO OOOOOO RD S T X 09 8 7 D6 5 43 2 1 0PPSAF
D A T A 1 5
D A T A 1 4
D A T A 1 3
D A T A 1 2
D A T A 1 1
D A T A 1 0
D A T A 9
8777 0987 /HOSTP8 /DTSExt /RESET /PWDN TestB TestA VDD VSS /PLLbypass CLKIN CLKOP VDD VSS SCLK RFS TFS DT DR IRQEx # MA11 SYSCLK 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
77777776666 65432109876
66666655555 54321098765
5555 4321 50 49 48 47 46 45 44 43 V DD DA T A 8 DA T A 7 DA T A 6 DA T A 5 DA T A 4 DA T A 3 DA T A 2 DA T A 1 DA T A 0 VSS D7 D6 D5 D4 D3 D2 /HPWR /HPRD D1
W62410
42 41 40 39 38 37 36 35 34 33 32 31
111111111122222222223 123456789012345678901234567890 E P P O 0 # / R A S E P S I O 0 # / C A S 0 E P S I O 1 # / C A S 1 EE PP SS II OO 23 ## // CC AA SS 23 / E P W R # / M W R E P P O 1 # EVE EEEE E PDP PPPP P PDP PPPP D O OOOO A O 3 4567 T 2 # #### A # M MM MM 4 MM A AAAA # AA 2 3456M 01 A 7 E P D A T A 5 # M A 8 E P D A T A 6 # M A 9 EVE EEEO PSP PPPS DS D DDDC A AAAI A T T TTN T A AAA A 0123 7 #### # M MMM M D DDD A 0123 1 0 O S C O P / D A C K / DV B0D Y D T E L H
/ E P R D # / M R D
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Preliminary W62410
BLOCK DIAGRAM
Example TAD Application
The figure below shows the basic block diagram for building a digital answering machine using the W62410 CHIPSET. In addition to the CHIPSET the following are needed:
* A Law CODEC. * DRAM of FLASH for use as external memory storage space. * A 4 or 8-bit Controller (using the serial port or 8-bit parallel port of the CHIPSET). * A 24.576 MHz crystal as the system clock for the CHIPSET. * A 32.768 KHz crystal for the Real Time Clock and to refresh the DRAM in Power Down mode. * Optionally an external OTP to disable the internal voice prompts, if preferred. * A DAA, user interface, microphone, loudspeaker, power supply, battery backup etc.
Analog
TP 3054 CODEC
DRAM or Flash
4x1Mx4 or 1x4Mx4 DRAM 4 x 4 MBits Flash 4 x 16 MBits Flash
Telephone Line Interface
Codec PIO
DRAM / Flash (ExtPort)
*Option for external voice stamp on-chip voice prompt support
DTS
Winbond OTP /DTSExt Serial/Parallel
16Kx16 DTS ROM
HIF
C Host *Host controls DAA and Front-End Operation
/PowerDown /Reset 32.768 KHz 24.576 MHz SYSCLK Power/Gnd TestA, TestB
DSP CORE
/HostP8 Timer RTC
System
DSP Bus I/F
User Interface Display/Key
Figure 2. W62410 Block Diagram
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Publication Release Date: April 2000 Revision A1
Preliminary W62410
PIN DESCRIPTION
Power and Clock
PIN NAME VDD GND OSCIN OSCOP ClkIN ClkOP SYSCLK RESET PWDN PIN NUMBER 10, 30, 50, 70, 87, 92 20, 40, 60, 80, 88, 93 25 26 90 91 100 83 84
I O I O O I I
I/O Power Ground
FUNCTION
32768 Hz Crystal Oscillator Input 32768 Hz Crystal Oscillator Output 24.576 MHz Crystal Oscillator Input 24.576 MHz Crystal Oscillator Output 24.576 MHz System Clock Output, while bit EnSYSCLK in TEST Reg. set, otherwise tri-state System hardware reset, internal pull high, schmitt trigger input Power low Indicator schmitt trigger input w/o pull high
Codec Interface
PIN NAME SCLK RFS TFS DR DT PIN NUMBER 94 95 96 98 97 I/O O O O I O FUNCTION Serial Clock at Serial Port, 2.048 MHz Receive frame sync. of Serial port Transmit frame sync. of Serial port Serial DATA received at Serial port Serial DATA transmitted at Serial port
PIO Interface
PIN NAME IO 0..15 PIN NUMBER 63, 64, 65, 66, 67, 68, 69, 71, 72, 73, 74, 7, 5, 76, 77, 78, 79 I/O I/O Bit I/O port Internal pull-up as input FUNCTION
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Preliminary W62410
HOST Interface
PIN NAME (Parallel) HostP8 PIN NAME (Serial) HostP8 PIN NUMBER 81 I/O I FUNCTION Host Selection Input Low for 8 bits parallel host mode High for serial host mode DACK ByteLH D[0] D[1] DACK ------HRdD HWrD HRdClk HWrClk ------27 28 29 31 32 33 34, 35, 36, 37, 38, 39 O/P I/P I/O I/O I/P I/P I/O Host acknowledge Parallel : Select low or high byte Parallel : Bi-directional data bit 0 Serial Serial
HPRD HPWR
: Host Read Data Out : Host write data In : Host read clock in : Host write clock in
Parallel : Bi-directional data bit 1 Parallel : Read strobe in Serial Serial Parallel : Read write in Parallel : Bi-directional data bit 2..7
D[2..7]
DRAM/Flash & Extension Port Interface
PIN NAME (DRAM) RAS CAS0 , 1, CAS2 , 3
MWR
I/O O O
PIN NAME (Flash) EPPO0 EPSIO[0..3]
I/O O I/O
PIN NUMBER 1 2, 3, 4, 5
DESCRIPTION DRAM: Row address strobe ExtPort: Extension parallel OP 0 DRAM: Column address strobe ExtPort: Extension serial IO [0..3] with internal pull up
O O O
EPWR
O O O I/O
6 7 8, 9, 11, 12, 13, 1, 4, 15, 16, 17, 18, 19
DRAM: DRAM write strobe ExtPort: Extension port write enable DRAM: DRAM Read strobe ExtPort: Extension port read enable DRAM: DRAM Address bus ExtPort: Extension parallel OP[1..7], Extension bit data port[4..7]
MRD MA[0..10]
EPRD EPPO[1..7] EPData[4..7]
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Publication Release Date: April 2000 Revision A1
Preliminary W62410
DRAM/Flash & Extension Port Interface, continued
PIN NAME (DRAM) MA[11] MD[0..3]
I/O
PIN NAME (Flash) IRQEx EPData[0..3]
I/O
PIN NUMBE R 99 21, 22, 23, 24
DESCRIPTION
O I/O
I I/O
DRAM : DRAM Address bit 11 ExtPort: Extension port interrupt DRAM: Data bus for DRAM controller ExtPort: Extension bit data port[0..3] Bi-directional I/O pin with repeater
DTS ROM Interface
PIN NAME DTSExt PIN NUMBER 82 I/O I FUNCTION DTS ROM selection, internal pull-up 1: Internal DTS ROM. In this mode the following 3 pins are of no use. 0: External DTS ROM Wrp Rdp OtpData 62 61 59 O/P O/P I/O Write Clock Pulse, active high Read Clock Pulse, active high Bi-directional Data Line
TEST Pins
PIN NAME PLLbypass PIN NUMBER 89 I/O I FUNCTION PLL bypass test mode for use in test machine only, internal pull up Low : Bypass PLL, High : Normal 4xF TestA TestB 58 86 85 O I Output, 4xClkIn, while bit En4xF in TEST Configuration Reg. set to high, otherwise tri-state Internal pull high, Test mode set Leave these pins NC in normal mode
CHIPSET BUS Interface:
PIN NAME DATA[0..15] PIN NUMBER 41, 42, 43, 44, 45, 46, 47, 48, 49, 51, 52, 53, 54, 55, 56, 57 I/O I/O Test pins FUNCTION
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Preliminary W62410
Booting Sequence
/Reset Test A,B
NC or 11
Booting
CODEC Interface
* The interface signals for the Law CODEC are: SCLK, RFS, TFS, DR and DT. * The relationship between SYSCLK and SCLK is as follows:
SCLK =
SYSCLK 2 * ( SCLKDIV + 1) 24,576,000MHz 2 * (5 + 1)
2,048MHz =
* Therefore, the value of SCLKDIV in the Init command should be set to five when using the
CHIPSET with a SYSCLK of 24.576 MHz. This results in a sampling rate of 8 KHz. The Receive frame sync (RFS) rate
2,048,000Hz = 8,000Hz . 256
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Publication Release Date: April 2000 Revision A1
Preliminary W62410
TIMEING WAVEFORMS
CODEC Timing
CODEC interface Transmit Timing 2.048MHz
SCLK 8KHz TFS
DT triggered by writing TX reg
B7
B1
B0
CODEC interface Receive Timing 2.048MHz
SCLK 8 KHz RFS
DR H/W generated free running signal
B7
B6
B0
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Preliminary W62410
DRAM as External Storage Memory
Selecting DRAM: The following types of DRAM are allowed: Type 1M x 4 4M x 4 4M x 4 DRAM Refresh: * The DRAM controller uses CAS-BEFORE-RAS (CBR) in a distributed way at every 15.625 S. There are two different refresh modes available in the DRAM controller: Normal Mode: While in normal operation, the DRAM controller the refresh request is determined by the value of REFDIV and of the SYSCLK. The exact formula can be found below: Row MA 0..9 MA 0..10 MA 0..11 Column MA 0..9 MA 0..10 MA 0..9
1000 * (REFDIV + 1) = refreshper iod = 15.625 S 24.576
Thus, the REFDIV value controls the refresh period. The default value is 383. 32768 Mode: While in Power Down mode, the DRAM controller generates the refresh request at the frequency of 2 times 32,768 Hz, or about every 15.3 S.
Refresh Mode in different operation conditions
POR /RESET Refresh None Mode Operation reset Condition Normal run Enable DRAM 32768 power down reset Normal run
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Publication Release Date: April 2000 Revision A1
Preliminary W62410
DRAM Normal Read Cycle
T1 SYSCLK /RAS /CAS MA MD /MRD /MWR ROW
T2
T3
T4
T5
T6
T7
T8
T9
COL
ROW
Tcas
Data Latch In
DRAM Early Write Cycle
T1
T2
T3
T4
T5
T6
T7
T8
T9
SYSCLK /RAS /CAS MA MD /MRD /MWR ROW COL ROW
DRAM Normal CBR Refresh Cycle
T1
T2
T3
T4
T5
T6
T7
T8
T9
SYSCLK /CAS /RAS MA MD /MRD /MWR ROW High-Z
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Preliminary W62410
DRAM CBR Refresh Cycle
/PWDNACK /CAS /RAS MA MD /MRD /MWR ROW High-Z
FLASH as External Storage Memory
Flash interface (extension port)
DMAaddr /RD /WR EnExt
Extension Port MMP
/EPRD /EPWR
DMD[7..0] en
EPData[7..0]
D
Q en_sio
EPPO[7..0]
D
Q
EPSIO[3..0]
IRQ_EX
AND EnExt
Sync
IRQEx
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Publication Release Date: April 2000 Revision A1
Preliminary W62410
Flash Read Cycle
SYSCLK /EPRD EPData[7..0] T0 T1 T2 T3
Flash Write Cycle
SYSCLK /EPWR EPData[7..0] T0 T1 T2 T3
Using Flash
with the W62410
KM29N1600T
KM29N1600T KM29N040T IO[7..0]
CLE ALE /RE /WE
KM29N1600T KM29N040T IO[7..0]
CLE ALE /RE /WE
KM29N1600T KM29N040T IO[7..0] CLE ALE /RE /WE
W62410
EPData[7..0] EPPO[5..4] /EPWR, /EPRD
KM29N040T IO[7..0]
CLE ALE /RE /WE
R/Bn EPPO[0] EPPO[1] EPPO[2] EPPO[3] /CE /WP /CE
R/Bn /CE /WP
R/Bn /CE /WP
R/Bn /WP
VDD R
EPPO[6] IRQEx
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Preliminary W62410
External OTP Functional Waveform (for W55412 and W55412A)
The W62410 has the capability to use an external OTP instead of its own internal 256 KBits ROM for the storage of voice prompts. Below you can find the timing signals between the W62410 and either the W55412 or W55412A OTP.
WRP
1
2
17
18
A17
A16
A1
A0
D0
D1
D15
D0
D1
D15
DATA
/WR DTS Status RDP min 1s EnDTS Add
1
2
16
1
2
16
DTSAdd DTSData IRQ_DTSROM /RD DTS Data DRdy
Add+1 Data(Add)
Load DTS Data Generate IRQ
Note: A3, A2, A1, A0 is forced to Low for word alignment. A[17..4] = DTSAdd[13..0]
HOST Interface (HIF)
The W62410 allows connecting to the host controller through a serial or a 8 bits parallel (8051-like) port. The port is selected through the /HostP8pin: /HostP8pin Low High Selects 8-bit parallel (8051-like) interface Serial Controller interface
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Publication Release Date: April 2000 Revision A1
Preliminary W62410
8-bits Controller interface
8-bit parallel interface
/DACK /ByteLH Controller D[0..7] /RD, /WR /HostP8 LHSQ4808A
GND
8-bit parallel data transfer
/ByteLH D[0..7] /RD /WR Low Byte data High Byte data
* The Controller can send a command to the W62410 by writing the low byte first followed by the
high byte of the 16-bit command word.
* The Controller can read the 16-bit result from the W62410 by reading the low byte first followed by
the high byte after receiving a /DACK interrupt from the W62410 to indicate that there is data to be read. Serial Controller interface
Serial port
HWrClk HWrD HRdClk Controller HRdD /DACK Vdd /HostP8 LHSQ4808A
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Preliminary W62410
The host can write a 16-bit command in the following way:
* Check that the /DACK pin is set high to be sure you can send a new command to the W62410. *
The Controller has to toggle HWrClk and HWrD to send the 16-bit command to the Command Register of the W62410. The W62410 samples in the HWrD, with LSB first, at the falling edge of HWrClk. After having received 16 falling edges, the HWrClk returns to low and the complete 16-bit command has been stored in the command register of the W62410. The HIF asserts ComRdy and generates an IRQ_HOST inside the W62410. After the W62410 has read the 16-bit command, the ComRdy signal will return to the low state.
*
Serial Host Interface timing Host Write, HWrClk Normal Low
HWrClk /DACK HWrD D0 IRQ_HOST DSP RD ComRdy D1 D13 D14 D15
The host can read the 16-bit result in the following way:
* When the W62410 writes into the result register, then the DACK pin will be set low. * The ?Controller has to toggle the HRdClk to sample the HRdD. The ?Controller will receive the 16-
bit data with LSB first on the HRdD pin, at the falling edge of HRdclk. After 16 falling edges the complete result has been received, HRdClk returns to low and the DACK pin will be set high again.
Serial Host Interface timing Host Read, HRdClk in Normal Low
/DACK HRdClk
HRdD DSP WR Response IRQ_HOST
* D0 D1 D14 D15
*
Note * : Hi-Z
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Publication Release Date: April 2000 Revision A1
Preliminary W62410
PIO Controller
IO Port Configuration
Vdd R D15 DMD Dout PIO 15
Din
PWDN
* The I/O ports of IO 0..15 are bi-directional. * If user read the I/O port, the output latch will stay in tri-state mode and a weak pull high of about 40
A will be present to have data input.
* For the transition from write to read state, a dummy read is needed. * The I/O port will stay in output tri-state condition (including the pull high) during power down mode
and the input will be gated to avoid leakage current.
Power on Reset and H/W Reset
* The TAD provides an internal power on reset while power building up for the very first time (this is a
different situation than resetting the W62410 after putting the W62410 in Power down mode). The power on reset signal will force the Real Time Clock to be set to zero.
* To ensure that the system crystal oscillate properly, the reset signal must be kept low for at least
200 mS. This reset signal will not affect the memory nor the Real Time Clock Value.
Power Down Mode
* * * * *
Operation Current Idd < 80 mA at 5V IDLE mode Idd < 40 mA at 5V Power Down Mode < 100 A at 5V A low signal on the PWDN pin will invoke the highest priority interrupt vector to wake up the W62410. During power down, the system clock oscillating at 24.576 MHz, is stopped, except the Real Time Clock and DRAM refresh. The 32768 Hz oscillator will take over to support the Real Time Clock and the DRAM refresh control signals. The input/output pins will be kept in tri-state mode to isolate the DC path in power down mode. After PWDN release, a hardware reset signal must be activated again to let the W62410 wakeup and restart. - 16 -
* *
Preliminary W62410
*
In case of the use of Flash as external storage memory, power can be removed totally. The 32768 oscillator may be unnecessary, if Controller can maintain the Real Time Clock itself or is deemed unnecessary for the application.
Power-up Reset, Power-down, External H/W Reset
/PWDN Vdd R
/RESET
IRQ_PWDN to interrupt controller
Reset Logic
Internal H/W reset
Power On Reset
Power Down for DRAM Configuration
Vdd /RESET
POR
/PWDN
Power Down for Flash Configuration
Vdd /RESET POR /PWDN
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Publication Release Date: April 2000 Revision A1
Preliminary W62410
Master Crystal Oscillator Circuit (24.576 MHz)
CLKIN (90) 5V 100 KOhm 10 uF 2SA1015 CLKOP (91)
2200 Ohm
20p
24.567 MHz
20P
Real Time Clock Oscillator Circuit (32768 Hz)
OSCIN (25) OSCOP (26)
1000 Ohm
10p
32768 Hz
10P
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Preliminary W62410
ABSOLUTE MAXIMUM RATINGS
PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature SYMBOL VDD-VSS VIN TA TST MIN. -0.3 VSS -0.3 0 -55 MAX. +7.0 VDD +0.3 70 150 UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD-Vss = 5V 10%, TA = 25, CLKIN = 24.576 MHz, OSCIN = 32768 Hz)
PARAMETER Operating Voltage Operating Current Power Down Current
SYM. VDD IDD IPWD ILK1 ILK2
CONDITIONS MIN. Power Down Mode All except Pull high or low, tri-state, IRQEx internal pull high pin They are RESET , PLLbypass , TestA, TestB, 4.5 -10 -300
LIMITS TYP. MAX. 5.0 90 5.5 900 +10 +10
UNIT V mA iA
Input Leakage Current
iA
ILK3 Output Voltage Low Output Voltage High Input Voltage Low Input Voltage High Input Voltage Low Input Voltage High Input Voltage Low Input Voltage High VOL VOH VIL VIH VILS VIHS VILX VIHX
IRQEx Iol = 8 mA Ioh = -8 mA All except RESET , PWDN , OSC, CLK pin All except RESET , PWDN , OSC, CLK pin RESET , PWDN pin, Schmitt trigger input RESET , PWDN pin, Schmitt trigger input OSCIN, CLKIN pin, XTAL oscillator input OSCIN, CLKIN pin, XTAL oscillator input
-200 2.4 2.0 2.4 3.5
+100 0.45 0.8 0.8 1.5 V V V V
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Publication Release Date: April 2000 Revision A1
Preliminary W62410
PACKAGE DIMENSIONS
100L QFP(14 x 20 x 2.75 mm footprint 4.8 mm)
HD D
E
HE
e
b
c
A A2 See Detail F Seating Plane A1 y L L1
Controlling dimension: Millimeters
Dimension in inches Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
0.010 0.014 0.101 0.107 0.008 0.012 0.004 0.006 0.547 0.551 0.783 0.787 0.020 0.026 0.746 0.960 0.039 0.740 0.976 0.047 0.064 0.003 0 7 0 0.018 0.113 0.016 0.008 0.555 0.25 2.57 0.20 0.10 13.90 0.35 2.72 0.30 0.15 0.45 2.87 0.40 0.20
A A1 A2 b c D E e HD HE L L1 y
14.00 14.10 20.00 20.10 0.802
0.791 19.90 0.032 0.756 0.992 0.055
0.498 0.65 18.40 24.40 1.00
18.80 19.20 24.80 25.20 1.20 2.40 0.08 7 1.40
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Preliminary W62410
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886 -2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change withou t notice.
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Publication Release Date: April 2000 Revision A1

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